1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an elevated source/drain MOSFET structure in the fabrication of integrated circuits.
2. Description of the Prior Art
As devices are scaled down, short channel effects become severe. That is, as the dimensions of the gate are reduced, the threshold voltage of the MOSFET becomes less predictable. Short channel effects cause source/drain leakage and voltage roll-off. To prevent short-channel effects, shallow source/drain junctions must be used. However, shallow junctions cause problems when forming salicide, such as junction leakage. An elevated source/drain structure can reduce short channel effects without these problems.
A number of workers in the art have proposed elevated source/drain structures. U.S. Pat. Nos. 5,386,133 to Hiroki, 5,631,482 to Hong, and 5,684,319 to Hebert disclose methods of forming polysilicon spacers as source/drain contacts. U.S. Pat. No. 4,488,162 to Jambotkar shows a raised source/drain process.
A principal object of the present invention is to provide an effective and very manufacturable method of forming a MOSFET having an elevated source/drain structures.
A further object of the invention is to provide a method of forming a sub-quarter micron MOSFET having an elevated source/drain structure wherein short channel effects are reduced.
Yet another object is to provide a method of forming a sub-quarter micron MOSFET having an elevated source/drain structure wherein source/drains are extended by outdiffusion from the elevated source/drains.
In accordance with the objects of this invention a method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is achieved. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. The polysilicon spacers form elevated source/drain regions. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain extension regions underlying the elevated source/drain regions. The polysilicon spacer on an end of the gate electrode is removed to separate the elevated source/drain regions into an elevated source region and an elevated drain region thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.